- Series: Integrated Circuits and Systems
- Hardcover: 255 pages
- Publisher: Springer; 2007 edition (August 24, 2007)
- Language: English
- ISBN-10: 1402051875
- ISBN-13: 978-1402051876
- Product Dimensions: 6.5 x 0.7 x 9.4 inches
- Shipping Weight: 1.3 pounds (View shipping rates and policies)
- Average Customer Review: 2 customer reviews
- Amazon Best Sellers Rank: #10,919,640 in Books (See Top 100 in Books)
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Design for Manufacturability and Yield for Nano-Scale CMOS (Integrated Circuits and Systems) 2007th Edition
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From the Publisher
ASIC/ SOC designers, EDA R&D engineers, professors and graduate students
-CAD (Computer aided design)
-CAE (Computer aided engineering)
-DFM (Design for manufacturability)
-DFY (Design for yield)
-SOC (System on a chip design)
From the Back Cover
As we approach the 32 nm CMOS technology node the design and manufacturing communities are dealing with a lithography system that has to print circuit artifacts that are significantly less than half the wavelength of the light source used, with new materials, with tighter pitches, and higher aspect ratio metallurgies. This reality has resulted in three main manufacturability issues that have to be addressed: printability, planarization, and intra-die variability. Addressing in depth the fundamentals impacting those three issues at all the stages of the design process is not a luxury one can ignore. Manufacturability and yield are now one and the same and are no longer a fabrication, packaging, and test concerns; they are the concern of the whole IC community. Yield and manufacturability have to be designed in, and they are everybody’s responsibility.
Design for Manufacturability and Yield for Nano-Scale CMOS walks the reader through all the aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells and how to yield-grade libraries for critical area and lithography artifacts through place and route, CMP model based simulation and dummy-fill insertion, mask planning, simulation and manufacturing, and through statistical design and statistical timing closure of the design. It alerts the designer to the pitfalls to watch for and to the good practices that can enhance a design’s manufacturability and yield. This book is a must read book the serious practicing IC designer and an excellent primer for any graduate student intent on having a career in IC design or in EDA tool development.
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This book provides a good overview of the challenges in IC design for manufacturing and yield optimization.
It covers all the advanced problems at 65nm and below such as random and systematic variability, CMP and statistical design analysis.
The book represents an useful introduction to those topics for students, engineers and technical managers in the microelectronics industry.
The drawbacks are:
- very poor graphical quality of pictures and diagrams
- lack of an index
- some missing of relevant industrial examples (devices, metrics, analysis results)