- Paperback: 200 pages
- Publisher: Strawberry Canyon; 1 edition (November 7, 2017)
- Language: English
- ISBN-10: 0999249118
- ISBN-13: 978-0999249116
- Product Dimensions: 7.5 x 0.5 x 9.2 inches
- Shipping Weight: 1 pounds (View shipping rates and policies)
- Average Customer Review: 4 customer reviews
- Amazon Best Sellers Rank: #264,173 in Books (See Top 100 in Books)
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The RISC-V Reader: An Open Architecture Atlas Paperback – November 7, 2017
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About the Author
David Patterson retired after 40 years as a Professor of Computer Science at UC Berkeley in 2016, and then joined Google Brain as a distinguished engineer. He also serves as Vice-Chair of the Board of Directors of the RISC-V Foundation. In the past, he was named Chair of Berkeley’s Computer Science Division and was elected to be Chair of the CRA and President of the Association for Computing Machinery. In the 1980s, he led four generations of Reduced Instruction Set Computer (RISC) projects, which inspired Berkeley’s latest RISC to be named “RISC Five.” Along with Andrew Waterman, he was one of the four architects of RISC-V. Beyond RISC, his best-known research projects are Redundant Arrays of Inexpensive Disks (RAID) and Networks of Workstations (NOW). This research led to many papers, 7 books, and more than 35 honors, including election to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame as well as being named a Fellow of the Computer History Museum, ACM, IEEE, and both AAAS organizations. His teaching awards include the Distinguished Teaching Award (UC Berkeley), the Karlstrom Outstanding Educator Award (ACM), the Mulligan Education Medal (IEEE), and the Undergraduate Teaching Award (IEEE). He also won Textbook Excellence Awards (“Texty”) from the Text and Academic Authors Association for a computer architecture book and for a software engineering book. He received all his degrees from UCLA, which awarded him an Outstanding Engineering Academic Alumni Award.
Andrew Waterman serves as SiFive’s Chief Engineer and co-founder. SiFive was founded by the creators of the RISC-V architecture to provide low-cost custom chips based on RISC- V. He received his PhD in Computer Science from UC Berkeley, where, weary of the vagaries of existing instruction set architectures, he co-designed the RISC-V ISA and the first RISC-V microprocessors. Andrew is one of the main contributors to the open-source RISC-V-based Rocket chip generator, the Chisel hardware construction language, and the RISC-V ports of the Linux operating system kernel and the GNU C Compiler and C Library. He also has an MS from UC Berkeley, which was the basis of the RVC extension for RISC-V, and a BSE from Duke University.
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As an aside, part of Patterson's reason for gRISC architecture in the first place was a belief that complex instruction sets were more likely to have instruction set bugs. A few high-profile cases, the Pentium FDIV bug being just one, certainly corroborate that belief. The more recent Spectre and Meltdown vulnerabilities, though not directly related to CISC vs. gRISC issues, also point out how increasing processor complexity increases the chance of implementation problems.
I recommend this, not just to RISC-V programmers, but to anyone with an interest in modern processors. Although the RISC-V architecture is designed to be independent of any particular implementation, processor implementors will also find it very useful.