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Testing Semiconductor Memories: Theory and Practice
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Implementing embedded memory built in self-test (BIST) can alleviate these problems. In simplistic terms, memory BIST is an on-chip utility that enables the execution of a proven set of algorithmic style verification tests directly on the memory array. These tests can be executed at the design's full operating frequency to prove the memory array operations and identify errors caused by silicon defects.
Embedded memories are the most dense components within a system-on-chip (SOC), accounting for up to 90% of its real estate.1 Memories also are the most sensitive to process defects, making it essential to thoroughly test them in the SOCs.
Because memories are used as test vehicles for monitoring the silicon process and improving its yield, extracting additional diagnostic data to determine the causes of failures now is required in the testing strategy. In addition to diagnosis, many embedded memories are designed with built-in redundancy, which provides spare rows and columns that can replace failing locations. Redundancy enables the manufacturer to repair a number of otherwise defective devices to ensure maximum production yield.
Characteristics of today's SOC designs include the following:
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