- Hardcover: 320 pages
- Publisher: Star Galaxy Pub.; 2nd edition (August 1, 1998)
- Language: English
- ISBN-10: 0965039196
- ISBN-13: 978-0965039192
- Package Dimensions: 8.9 x 7 x 0.9 inches
- Shipping Weight: 13.6 ounces (View shipping rates and policies)
- Average Customer Review: 2 customer reviews
- Amazon Best Sellers Rank: #3,380,360 in Books (See Top 100 in Books)
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A VHDL Synthesis Primer, Second Edition Hardcover – August 1, 1998
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Customers who bought this item also bought
"I've learned about the subset of VHDL that a synthesis tool that we use synthesizes by trial and error over a year and a half, and this book would have saved me a lot of time" -- Andy Fingerhut, Washington University
"I don't think I have seen anyone cover VHDL synthesis in a general way as well as you have. I certainly think this will be a successful book" -- Rich Hatcher, Texas Instruments
"It (book) is an excellent treatment of VHDL synthesis and was quite helpful in understanding simulation/synthesis mismatches" -- Victor Berman, DASC Chair
"It (book) is very clear and concise; it is a good book and highly recommended" -- Doug Smith, VeriBest
"It (book) is well written and practical" -- Milan Gandhi, Indus Consulting
"The book gives a good impression what is, and is not synthesizable. Furthermore the influence of a VHDL description on the synthesis results is written in a clear way" -- Egbert Molenkamp, University of Twente, The Netherlands
"This (Bhasker's latest) book on VHDL Synthesis should be on the "Best Sellers List" in our mind. It's a well written text with plenty of examples to get you started in the right direction" -- William Billowitch, The VHDL Technology Group
From the Back Cover
Learn to Model for Synthesis using VHDL!
*See the details of how VHDL gets translated into logic gates in this book. *Also, see how hardware elements are described in synthesizable VHDL. *Over 100 illustrations and 3500 lines of VHDL code!
This book is a must primer for anyone who is beginning to learn synthesis using VHDL. A chapter on verification explains the many causes of simulation mismatches between pre and post synthesis models and on how to avoid these. Modeling guidelines are also provided to help improve synthesis results.
Top customer reviews
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It's useful both for beginners and practicing engineers.
This would be a must buy for students who would like
to start a career in VLSI, and also to those designers
who are not so familier with synthesis aspects of VHDL