Preface

During my earliest experience with Verilog HDL, I waslooking for a book that could give me a “jump start” on usingVerilog HDL. I wanted to learn basic digital design paradigms and the necessaryVerilog HDL constructs that would help me build small digital circuits, usingVerilog and run simulations. After I had gained some experience with buildingbasic Verilog models, I wanted to learn to use Verilog HDL to build largerdesigns. At that time, I was searching for a book that broadly discussed advancedVerilog-based digital design concepts and real digital design methodologies.Finally, when I had gained enough experience with digital design andverification of real IC chips, though manuals of Verilog-based products wereavailable, from time to time, I felt the need for a Verilog HDL book that wouldact as a handy reference. A desire to fill this need led to the publication ofthe first edition of this book.

It has been more than six years since the publication of thefirst edition. Many changes have occurred during these years. These years haveadded to the depth and richness of my design and verification experiencethrough the diverse variety of ASIC and microprocessor projects that I havesuccessfully completed in this duration. I have also seen state-of-the-artverification methodologies and tools evolve to a high level of maturity. TheIEEE 1364-2001 standard for Verilog HDL has been approved. The purpose of thissecond edition is to incorporate the IEEE 1364-2001 additions and introduce toVerilog users the latest advances in verification. I hope to make this editiona richer learning experience for the reader.

This book emphasizes breadth rather than depth. The bookimparts to the reader a working knowledge of a broad variety of Verilog-basedtopics, thus giving the reader a global understanding of Verilog HDL-baseddesign. The book leaves the in-depth coverage of each topic to the Verilog HDLlanguage reference manual and the reference manuals of the individualVerilog-based products.

This book should be classified not only as a Verilog HDLbook but, more generally, as a digital design book. It is important to realizethat Verilog HDL is only a tool used in digital design. It is the means to anend—the digital IC chip. Therefore, this book stresses the practicaldesign perspective more than the mere language aspects of Verilog HDL. WithHDL-based digital design having become a necessity, no digital designer canafford to ignore HDLs.

Who Should Use This Book

The book is intended primarily for beginners andintermediate-level Verilog users. However, for advanced Verilog users, thebroad coverage of topics makes it an excellent reference book to be used inconjunction with the manuals and training materials of Verilog-based products.

The book presents a logical progression of Verilog HDL-basedtopics. It starts with the basics, such as HDL-based design methodologies, andthen gradually builds on the basics to eventually reach advanced topics, suchas PLI or logic synthesis. Thus, the book is useful to Verilog users withvarying levels of expertise as explained below.

• Students in logic design courses at universities

Part 1 of this book is ideal for a foundation semestercourse in Verilog HDL-based logic design. Students are exposed to hierarchicalmodeling concepts, basic Verilog constructs and modeling techniques, and thenecessary knowledge to write small models and run simulations.

• New Verilog users in the industry

Companies are moving to Verilog HDL-based design. Part 1 ofthis book is a perfect jump start for designers who want to orient their skillstoward HDL-based design.

• Users with basic Verilog knowledge who need to understand advanced concepts

Part 2 of this book discusses advanced concepts, such asUDPs, timing simulation, PLI, and logic synthesis, which are necessary forgraduation from small Verilog models to larger designs.

• Verilog experts

All Verilog topics are covered, from the basic modelingconstructs to advanced topics like PLIs, logic synthesis, and advanced verificationtechniques. For Verilog experts, this book is a handy reference to be usedalong with the IEEE Standard Verilog Hardware Description Language referencemanual.

The material in the book sometimes leans toward anApplication Specific Integrated Circuit (ASIC) design methodology. However, theconcepts explained in the book are general enough to be applicable to thedesign of FPGAs, PALs, buses, boards, and systems. The book uses Medium ScaleIntegration (MSI) logic examples to simplify discussion. The same conceptsapply to VLSI designs.

How This Book Is Organized

This book is organized into three parts.

Part 1, Basic Verilog Topics, covers all information that anew user needs to build small Verilog models and run simulations. Note that inPart 1, gate-level modeling is addressed before behavioral modeling. I havechosen to do so because I think that it is easier for a new user to see a 1-1correspondence between gate-level circuits and equivalent Verilog descriptions.Once gate-level modeling is understood, a new user can move to higher levels ofabstraction, such as data flow modeling and behavioral modeling, without losingsight of the fact that Verilog HDL is a language for digital design and is nota programming language. Thus, a new user starts off with the idea that Verilogis a language for digital design. New users who start with behavioral modelingoften tend to write Verilog the way they write their C programs. They sometimeslose sight of the fact that they are trying to represent hardware circuits byusing Verilog. Part 1 contains nine chapters.

Part 2, Advanced Verilog Topics, contains the advancedconcepts a Verilog user needs to know to graduate from small Verilog models tolarger designs. Advanced topics such as timing simulation, switch-levelmodeling, UDPs, PLI, logic synthesis, and advanced verification techniques arecovered. Part 2 contains six chapters.

Part 3, Appendices, contains information useful as areference. Useful information, such as strength-level modeling, list of PLIroutines, formal syntax definition, Verilog tidbits, and large Verilog examplesis included. Part 3 contains six appendices.